With the development of integrated circuit technology, the feature sizes of semiconductor devices are getting smaller and smaller. Current complementary metal-oxide semiconductor (CMOS) devices use a high dielectric-constant (high-k) material as the gate dielectric layer and a metal as the gate electrode (HKMG).
For NMOS and PMOS devices, the expected work function of the metal gate is quite different, which is about 4.1 eV to about 4.4 eV and about 4.8 eV to about 5.1 eV, respectively. In the prior art, in order to obtain a work function of the metal gate suitable for NMOS and PMOS devices, different types of metal materials (different work functions) are generally used for metal gates of NMOS and PMOS devices. However, this increases the challenge and limitation of the material selection and associated processes. Further, in the case where the NMOS and PMOS devices have interconnected gates and are relatively close to an electric circuit, e.g., a static random access memory (SRAM), different types of metal gate materials between the NMOS and PMOS devices are very prone to cross-diffusion between the metal gates, resulting in an abnormal threshold voltage.
Therefore, it is desirable to ensure a proper metal gate work function. Further, in the case of CMOS devices, it is also desirable to form metal gates having dual work functions and there is no cross-diffusion between the dual work functions of the metal gates.
Additionally, it is desirable to enable a semiconductor device to obtain a lower equivalent oxide thickness (EOT) and to reduce the gate leakage current. In conventional processes, a gate dielectric layer typically includes an interface layer (IL) and a high dielectric-constant dielectric layer. In order to obtain a lower EOT, it is necessary to reduce the physical thickness of the interface layer and/or the high dielectric-constant dielectric layer. However, this results in an increase in the gate leakage current. Thus, it is desirable to obtain a lower EOT without reducing the physical thickness of the gate dielectric layer.